| 摘要 |
A combination multiplier/shifter circuit (FIG. 2) can be used to implement an arithmetic or execution unit, using the multiplier/shifter to perform both multiplication operations and shift operations (such as for alignment or normalization). The arithmetic unit includes separate multiplier and adder channels. The multiplication channel includes a Multiplier/Shifter Circuit (10) with both multiplication and shift logic. The multiplication logic comprises an Adder Tree 12 with a rectangular aspect ratio (71x12) and Booth Recoder Logic 14, and implements conventional Booth recoded multiplication. The shift logic comprises Shift Control Logic 20 and Shift Extender Logic 32. For multiplication operations, redundant partial/final products MS1 and MS2 (sum and carry) are generated as the multiplication output, with conversion to nonredundant partial products, and the addition of partial products to obtain a final product, being performed in the adder channel. For shift operations, right and left variable shift operations of 0-16 bits are implemented in response to a 5 bit shift count, with the Multiplier/Shifter Circuit performing variable right shifts of 0-16 bits (such as for alignment)-variable left shifts of 0-16 bits (such as for normalization) are performed by first performing an 8 or 16 bit fixed left shift using separate shift logic, and then if necessary, shifting back right by a variable amount in the Multiplier/Shifter Circuit.
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