Method and apparatus for adaptive clock deskewing

摘要

A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors. The proximal end of one of the pair of conductors is coupled to the output of a delay line and receives a phase corrected version of the system clock signal. The distal end of this conductor is coupled to the load device at a clock connection node. The clock connection node is fed back to the phase correction circuit via the other one of the pair of conductors. The first and second conductors have equal path lengths in order to provide equal propagation delays. The clock signal fed back from the load device node is coupled as a feedback input to a three input phase detector circuit. The other two inputs are the clock signal output from the phase correction circuit delay line and the system clock signal. Each phase correction circuit includes a charge pump coupled to the output of the phase detector circuit, and a loop filter coupled to the output of the charge pump. The output of the loop filter is coupled to the input of the delay line. Each phase correction circuit is identically configured and the system clock signal is commonly provided to both the input of the phase detector in each phase correction circuit and a delay line clock reference input.