发明名称 Circuit to control locks in multi-cache shared memory computer system
摘要 The lock control stores the state of a lock variable for each processor in the computer system and for each memory bank of the system. The state of the variable is controlled so that if the state of the lock variable in one bank shows a lock acquisition state, the lock variable of all the other banks is set to the acquisition state. The lock variable has a first state that indicates when a cache has acquired the lock and other caches have not, and a second state to indicate that the cache memory associated with the lock controller has not acquired the lock, and that it is not certain that other caches have acquired the lock. A third state indicates no cache has acquired the lock, and a fourth state indicates that another cache has acquired the lock.
申请公布号 FR2733067(A1) 申请公布日期 1996.10.18
申请号 FR19960004662 申请日期 1996.04.15
申请人 NEC CORPORATION 发明人 MATSUMOTO KAZUYA
分类号 G06F12/00;G06F9/46;G06F9/52;G06F12/08;(IPC1-7):G06F12/08;G06F15/80 主分类号 G06F12/00
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