发明名称 |
Microcomputer with multiple CPU'S on a single chip with provision for testing and emulation of sub CPU's |
摘要 |
A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside. |
申请公布号 |
US5566303(A) |
申请公布日期 |
1996.10.15 |
申请号 |
US19940251556 |
申请日期 |
1994.05.31 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TASHIRO, TETSU;CHO, YOSHIKI |
分类号 |
G06F11/28;G01R31/317;G06F11/22;G06F11/26;G06F11/273;G06F15/78;(IPC1-7):G06F13/00 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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