| 摘要 |
<p>PURPOSE: To reduce the power consumption by eliminating unnecessary high- speed operation. CONSTITUTION: This clock signal distributing device consists of clock signal transmission parts 12 and 14 which send a clock signal CLK and a clock signal reception part 56 which receives the clock signal CLK. This clock signal reception part 56 is provided with an abnormality detecting circuit 58 which detects abnormality of the clock signal CLK and a reception-side selector circuit 60 which selects a normal clock signal transmission part 12 or 14 according to the detection result of the abnormality detecting circuit 58. The clock signal transmission part 12 is provided with a frequency dividing circuit 16 which divides the frequency of the clock signal CLK, and a transmission-side selector circuit 20 which sends the clock signal CLK as it is when the clock signal transmission part 12 is selected and transmits the clock signal CLK through the frequency dividing circuit 16 when the clock signal transmission part 12 is not selected.</p> |
