| 摘要 |
PURPOSE: To enable a high grade data transmission by performing the carrier phase correction for every time slot and switching from a delay detection to a synchronization detection. CONSTITUTION: A reception is performed by a delay detection when communication is started, a symbol delay device 27a obtaining a symbol rate delay in a delay part 27 is selected by a switch 27b and the reception is outputted to a phase circuit 29. At the both ends of the circuits 29, a phase difference of π/2 for an intermediate frequency is generated. But, when the reception carrier frequency from each terminal is shifted, a phase error is generated in the both- end phases of the circuit 29. This error is corrected by imparting the serial data columns at the both ends of the circuit 29 to a phase comparator 55 and imparting the output to a VCO 61 via a low-pass loop filter 57 and a switch 59, and the phase shift amount of the circuit 29 is limited and stabilized. The output of the filter 57 is imparted to also a synchronizing detector 63, and plural symbols periods and the output of the filter 57 are observed at this detector. In the case of a synchronization, each switch is controlled to a synchronizing detection operation mode via a timing generation part 45. |
