LOCAL BUS ARBITRATION APPARATUS AND METHOD

摘要

The apparatus is for arbitrating the local bus of a CPU board in a multi-processor system equipped with cache. The apparatus comprises: a CPU(60) equipped with cache and operating as cachable access and non-cachable access; controlling devices operating as a local bus master; a local bus arbiter(61) controlling local bus occupancy by the signal from the CPU(60); a CPU interface(64) controlling the data access of the CPU(60); a data transmission controller accessing the data of a main bus; a lock signal generator(66) generating lock signal for suspending the local bus occupancy of the CPU; a free signal generator(67) generating the free signal for retrying the local bus occupancy of the CPU(60); and a retry information storing device(65) transmitting retrying signal to the CPU(60).