| 发明名称 |
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| 摘要 |
PURPOSE:To simplify the interruption processing having an unfixed running level by securing such a mechanism where the interruption signal of the highest level is detected by an AND of an interruption request signal and an interruption factor signal and an external interruption permission flag is invalidated. CONSTITUTION:An interruption level deciding circuit 4 decides the highest interruption level by an AND of the interruption request signal supplied to a microprocessor MPU1 and an interruption factor signal (Au). An invalidating circuit 6 invalidates an external permission flag 2 when an interruption signal LV7 of the highest level is detected by the circuit 4. A flip-flop (FF)5 holds the signal that secured an AND between the output signal of the circuit 6 and the signal (An). Thus it is possible to simplify the interruption processing having an unfixed running level through software with no consciousness of the present interruption level. At the same time, a common mask operation is secured at an optional interruption level. |
| 申请公布号 |
JP2538885(B2) |
申请公布日期 |
1996.10.02 |
| 申请号 |
JP19860189338 |
申请日期 |
1986.08.12 |
| 申请人 |
FUJITSU KK;PII EFU YUU KK |
发明人 |
SAIDA MASAHIRO;KATAKURA OSAMU;OKABE KAZUYOSHI;SUGAWARA HIDEYUKI;KISHIMOTO HIROYUKI |
| 分类号 |
G06F9/48;G06F13/24;(IPC1-7):G06F9/46 |
主分类号 |
G06F9/48 |
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