| 摘要 |
A method and apparatus for reducing the effective latency for nonsequential memory accesses is disclosed. An improved cache includes a multi-stage pipelined cache that provides at least one cache output record in response to a record address hitting the pipelined cache. The pipelined cache provides the record after an idle period of L clock cycles in which the pipelined cache provides no output records. The effective latency of the pipelined cache is reduced by providing a branch target cache (BTC) that issues at least one record during the idle period in response to a nonsequential record address hitting the BTC. The records stored in the caches may, for example, represent instructions. The cache further includes a lookahead circuit for providing the nonsequential record address (A) and a lookahead address (A+(LxW), where W denotes the issue width) to the pipelined cache during a zero cycle preceding the idle period. The pipelined cache respectively provides a nonsequential record and a lookahead record from the lookahead address after the idle period in response to the nonsequential record address and the lookahead address hitting the pipelined cache. A multiplexer selects the nonsequential record from the pipelined cache as an output if the nonsequential address misses the BTC. The multiplexer selects the lookahead record as the output if the nonsequential address hits the BTC. Various modifications of this technique are also described. |
