Memory element of the master-slave type implemented in CMOS-technology

摘要

The element includes a master section which is formed from two-stage logic with p-channel and n-channel supply voltages. The first stage provides a logic output dependent on the clock signal (CK) and AND logic (A) as a logic variable (B). A simple NAND port converts the logic to a variable (A). The variable is used in a slave section to set the slave logic to the master logic. This is carried out by a two-stage section, the first stage takes the true output (Q) and the input logic (A) to provide a logic state (NQ). The second stage is a NAND gate which provides the true logic state (Q).