| 摘要 |
An apparatus for and method of providing a system whereby a number of processors may communicate with a memory device and wherein the memory device may operate at a slower speed without substantially reducing the band pass of the computer system. Further, one or more of the processors may have a different data word width from the other processors and from the memory device. The present invention may minimize the amount of wasted memory bits contained therein by concatenating data words such that the resulting data word substantially matches the word width of the memory device. The present invention further allows predefined portions of a data word to be placed in an order and concatenated with predefined portions of the same data word or with predefined portions of other data words. A number of predetermined formats define the selection and the order that the predefined portions may be placed. Various formats are contemplated and are described herein.
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