| 摘要 |
PURPOSE: To obtain a DRAM which can realize large reduction of power consumption, high reliability, and increasing speed securing quantity of read-out signals equal to or more than that of conventional read-out signals. CONSTITUTION: This device is a DRAM provided with a cell array in which plural bit line pairs and plural word lines are arranged crossing and a memory cell is provided at each crossing part. The memory cell M consists of a transistor QM and a capacitor CM, a gate of the transistor QM is connected to a word line WL, a drain is connected to one, BL1, of a pair of bit lines, a source is connected to a first terminal, a second terminal of the capacitor CM is connected to the other, BL2, of the pair of bit lines. At the time of sensing, amplitude of a bit line potential is set to one third or less of a difference between Vcc and Vss so that potential variation of a storage node SN of a memory cell MC is in a range of Vcc and Vss. |
