发明名称 DECENTRALIZED CONTROL SYSTEM IN MICROPROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a dispatch completion control mechanism which maintains a complicated control subordinate relation between instructions in a super-scalar processor without being assigned with cycle time in connection with a large serial queue structure. SOLUTION: Although global buses exist, none of the buses is limited in cycle (in general, most of the buses are latch-to-latch paths). The merit of this completion control mechanism is many tag bits related to each instruction stage. When viewed from the area reduction of lithography, however, the merit is small and a newer more powerful technology can be used.
申请公布号 JPH08241213(A) 申请公布日期 1996.09.17
申请号 JP19960008029 申请日期 1996.01.22
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 KURISUTOFUAA HANSU ORUSON;TERENSU MAZEU POTAA;MAIKERU TOOMASU BADEN
分类号 G06F9/46;G06F9/38;(IPC1-7):G06F9/46 主分类号 G06F9/46
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