A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when another of the bus lines is held in a logic high state.
申请公布号
AT141734(T)
申请公布日期
1996.09.15
申请号
AT19900901399T
申请日期
1989.12.21
申请人
MOTOROLA, INC.
发明人
WILSON, GREGORY, P.;POTRATZ, BRYAN, A.;WALCZAK, THOMAS, J.;MULLINS, JEFFREY, L.