| 摘要 |
<p>PURPOSE: To suppress potential fluctuations of bit lines at the time of writing of data in memory cells of an EEPROM. CONSTITUTION: The drain of a memory cell transistor Ma1 is connected to the subbit line BLsa1 of the EEPROM, The subbit line is connected to a latch circuit 30a via a connection transistor Tga. The potential of the subbit line corresponding to data stored in the memory cell transistor Ma1 is latched by the latch circuit 30a. By this latch, the potential of the subbit line is held at a fixed value corresponding to the memory cell storage data.</p> |
