| 摘要 |
In order to rapidly acquire and track a clock signal embedded in a reduced length synchronization preamble, a bit synchronizer contains a digital counter, which counts clock signals from a local clock generator having a frequency that is a multiple of the frequency of the data modulations in the received signal. The inverse of the most significant bit output of the counter sources the regenerated clock signal. In response to transitions in the monitored signal, the contents of the counter are coupled to an accumulator to provide successive measures of the (phase) difference between the times of occurrence of the regenerated clock signal and the actual times of occurrence of the sync preamble transitions. The contents of the accumulator are averaged over a prescribed number of monitored transitions and the resulting average is coupled to comparator, which compares the phase difference average output of the accumulator with the contents of the counter. When the phase difference average coincides with the contents of the counter, the counter is reset, thereby aligning the phase of the regenerated clock with that of the monitored signal. In addition, as the accumulator is updated, its input values from the counter are made available over a separate dedicated output link, to permit an attendant communications control processor to monitor the tracking performance of the apparatus.
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