发明名称 Data flow processor with variable logic connection between processors in a system
摘要 A data flow processor 10 having a plurality of input ports INA and INB, and a plurality of output ports A and B, includes an input unit 12, an operation unit 14, a branching unit 16, and a branching control parameter register group 18. Input unit 12 applies a packet directed to operation unit 14 and other packets to branching unit 16. Operation unit 14 conducts a prescribed operation to the data packet, and applies a resultant packet to branching unit 16. Branching unit 16 stores a branching control parameter in a previously applied packet in a prescribed format in register group 18. Branching unit 16 compares a prescribed parameter included in the input packet and the branching control parameter stored in branching control parameter register group 18, and outputs the packet to one of ports A and B based on the result of comparison. A plurality of such data flow processors 10 are prepared, their input ports and output ports are connected with each other, and then data packets for setting the branching control parameters for the processors are sequentially applied and thus logical connection between the data flow processors is determined.
申请公布号 US5555386(A) 申请公布日期 1996.09.10
申请号 US19950397720 申请日期 1995.03.02
申请人 SHARP KABUSHIKI KAISHA 发明人 NOMURA, SHINGO
分类号 G06F15/82;G06F9/44;(IPC1-7):G06F7/04;G06F13/00 主分类号 G06F15/82
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