发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE: To reduce output phase fluctuation in the operation of repulling-in by minimizing phase difference generated in the case of switching a reference signal. CONSTITUTION: When a reference signal CK1 is interrupted longer than a fixed term, a phase compared result deciding circuit 52 outputs an asynchronous detecting signal, an input interruption detecting circuit 40 outputs a switching signal so that a reference signal CK2 can be switched and outputted by a selector 30, and a switch control circuit 53 controls the opening of a switch 54 by inputting the switching signal and the asynchronous detecting signal so that the reference signal CK2 can be prevented from being supplied to a phase locked loop(PLL). When the phase difference between the reference signal CK2 and a frequency divided clock gets lower than a cancel level soon, the phase compared result deciding circuit 52 stops outputting the asynchronous detecting signal, the switch control circuit 53 controls the short-circuiting of the switch 54 by stopping inputting the asynchronous detecting signal so that the reference signal CK2 can be supplied to the PLL, and timing to start the operation of synchronization to the new reference signal can be controlled.
申请公布号 JPH08228149(A) 申请公布日期 1996.09.03
申请号 JP19950033800 申请日期 1995.02.22
申请人 TOSHIBA CORP 发明人 TAKAMI MASAYUKI
分类号 H03L7/00;H03L7/087;H03L7/14 主分类号 H03L7/00
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