Non-etchback self-aligned via size reduction method employing ozone assisted chemical vapor deposited silicon oxide

摘要

A method for forming a narrow cross-sectional diameter via through an insulator layer for use within an integrated circuit. Formed upon a semiconductor substrate is a metal layer. At least the top surface of the metal layer is formed from a titanium nitride layer. Formed upon the titanium nitride layer is an insulator layer. The insulator layer exhibits a first incubation time with respect to forming an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating upon the insulator layer. The first incubation time is less than a second incubation time for forming the same ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating upon the titanium nitride layer. A conventional via is then formed completely through the insulator layer. The bottom of the conventional via exposes a portion of the titanium nitride layer. Formed upon the surface of the insulator layer and upon the edges of the insulator layer exposed within the conventional via is an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating. The ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating is deposited for a deposition time greater than the first incubation time, but no greater than the second incubation time.