发明名称 I/O EQUIPMENT CONTROLLER
摘要 <p>PURPOSE:To improve the processing efficiency of a system by causing an external power supply detecting circuit to recognize the state of a RAM in a storage controller before a CPU accesses an external storage device and when the RAM is instable, initializing the RAM. CONSTITUTION:A CPU 10 sends an address signal 40 and control signal 41 before accessing an external storage device H/D 50 and an address decoder 31 sends a read strobe signal to a control register 61 in an external power supplying state detecting circuit 60. Therefore, data of the state of external power supply are sent to a data bus 42 from the register 61 and the CPU 10 and recognize the state of a RAM for data buffer by fetching the data. When the RAM is instable, the CPU 10 accesses the external storage device H/D 50 after setting the device H/D 50 to an accessible state by performing an initializing process and producing the command information and data check bits of the RAM for data buffer. Therefore, the processing efficiency of this system can be improved.</p>
申请公布号 JPH01161560(A) 申请公布日期 1989.06.26
申请号 JP19870318890 申请日期 1987.12.18
申请人 HITACHI LTD 发明人 TERAKADO YASUHIRO
分类号 G06F13/12;G06F1/00;G06F1/28 主分类号 G06F13/12
代理机构 代理人
主权项
地址