发明名称 |
Address generating circuit of a two-dimensional coding table |
摘要 |
An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log2S<P and P is a positive integer); comparators which examine whether the inputted y satisfies x+log2y</=P for each integral number of x, and examine whether the inputted x satisfies y+log2x</=P for each integral number of y; an escape signal generation section which outputs an escape signal according to the output of the coincidence detectors and the comparators; an address generation section which generates and outputs an address signal from values x and y and an identification address for identifying that x and y are integers; a priority control section which inputs the output from the coincidence detectors, determines which signal is outputted with precedence and outputs it; and a multiplexer which selects and outputs an address signal in accordance with the output from the priority control section.
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申请公布号 |
US5553257(A) |
申请公布日期 |
1996.09.03 |
申请号 |
US19940189680 |
申请日期 |
1994.02.01 |
申请人 |
NEC CORPORATION |
发明人 |
ISHIDA, HIDEO;OOI, YASUSHI |
分类号 |
H03M7/42;H04N7/26;H04N7/30;(IPC1-7):G06F12/00 |
主分类号 |
H03M7/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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