发明名称 ANALOG MONITORING CIRCUIT FOR DIGITAL RELAY
摘要 PURPOSE: To prevent erroneous function of an analog monitoring circuit due to fluctuation of frequency by comparing a current sampling data subjected to A/D conversion with a data sampled predetermined cycles before and locking the output of a decision circuit for comparing the negative phase sequence component with a decision level when the difference exceeds a predetermined level. CONSTITUTION: A difference appears between a sampling data at current moment of time and a data sampled one or more integer cycles of basic frequency before as the frequency varies. A monitoring/locking circuit 3 detects the difference and delivers a signal when the difference exceeds a predetermined level. Since a negative phase sequence component detection circuit 1 detects the negative phase sequence component using the current value of sampling data and data sampled 4 (120 deg.) and 8 (240 deg.) samples before, the circuit 1 detects an apparent negative phase when the frequency varies. A decision circuit 2 delivers a signal when the detection value exceeds a predetermined level. Since the monitoring/locking circuit 3 is delivering a signal at that time, an AND circuit 4 locks the output of the decision circuit 2.
申请公布号 JPH08223774(A) 申请公布日期 1996.08.30
申请号 JP19950026706 申请日期 1995.02.15
申请人 MEIDENSHA CORP 发明人 YAMADA YUTAKA
分类号 H02H3/02;H02H3/05 主分类号 H02H3/02
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