| 摘要 |
PURPOSE: To stabilize the operation of a detection circuit and to detect a signal to be synchronized with high efficiency by storing the state of the signal to be synchronized preceding its level change detecting section. CONSTITUTION: The internal clock CLK is supplied to the 1st and 2nd flip-flops 1 and 2, and the signal A to be synchronized is inputted to a terminal d1 of the flip-flop 1 and also to one of both input terminals of an AND gate 4. At the same time, the storage signal R0 is inputted to the clock enable terminal ce1 of the flip-flop 1 in order to store the preceding state of the detecting section of the signal A. Then the rise detection signal C which detects the trailing edge of the signal A is kept in a HIGH state. As a result, the level change of the signal A can be detected in its detecting section even if the signal A has a level change in a period shorter than the set-up time of the flip-flop 2 and right before the change of the clock CLK. |
