| 摘要 |
PURPOSE: To suppress increase/decrease in a potential difference due to parasitic resistance of a digit line pair and to uniformize and accelerate a read-out delay time by providing a transistor controlling with a control signal taking logic between a write/read-out switch signal and a row address signal on the digit line pair. CONSTITUTION: A transistor TK01 connected between the digit line pair DL, DLB is provided in the load transistors TL01-TL04 side ends of the digit line pair DL, DLB. The transistor TK01 is one for clamping the potential difference between the digit line pair DL, DLB. The gate is connected to a clamp control signal RK generated by prescribed logic operation between the write/read-out switch signal and a row address signal selecting optional one connected to the digit line pair DL, DLB. Thus, by the parasitic resistance R1 of the digit line pair, the increase of the amplitude of the digit line pair depending on a position of a selected memory cell on a digit line is suppressed, and the delay of the read-out delay time is reduced and accelerated. |
