| 摘要 |
<p>A high-performance processor, such as a central processing unit (CPU) (51), that includes structure and methods for providing numerous special processor features and capabilities is disclosed. These structures and methods include, but are not limited to, structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; maintaining and restoring precise state at any instruction boundary; (2) tracking instruction status to maintain precise state; (3) checkpointing instructions to maintain precise state; (4) creating, maintaining, and using a time-out checkpoint; (5) tracking floating-point exceptions; (6) creating, maintaining, and using a renamable trap-stack; (7) creating, maintaining, and using a Watchpoint for plural simultaneous unresolved branch evaluation; (8) tracking instruction status to maintain precise state; and (9) increasing processor throughput while maintaining precise state.</p> |
