| 摘要 |
PURPOSE: To momently extract the phase or a clock signal against a burst input data signal by taking the invertion signal of exclusive OR between an input data signal and data, which is obtained by delaying the input data signal by a specific period phase of the transmission rate, as a gating signal. CONSTITUTION: A delay circuit 11 which delays the input data signal by a 1/2 period phase of the transmission rate and an exclusive OR circuit 12 which takes exclusive OR between the signal delayed in this manner by the delay circuit 11 and the input data signal are provided. A logic inverting circuit 13 which inverts the output signal of the exclusive OR circuit 12 to output the gating signal and a voltage controlled oscillator 20 which controls oscillation by the gating signal are provided. Thus, the clock signal can be continuously sent even at the time of continuity of the same code. Consequently, the phase of the clock signal is momently extracted against burst input. |
