| 摘要 |
PURPOSE: To prevent the performance from deteriorating during normal operation by realizing a free regular scanning operation using a scanning circuit. CONSTITUTION: Transfer gates 3, 4 are inserted into the way of output signal lines from a NOR circuit 1 and a NAND circuit 2 to be scanned. The transfer gates 3, 4 are connected, on the output side thereof, with transfer gates 5, 7. The transfer gate 5 is interrupted when a clock ϕ1 is '0' and an output signal A from the NOR circuit 1 is placed on the output signal line thereof. The transfer gate 5 is conducted when the clock ϕ1 is '1' and an inputted scan-in signal IN is placed on the output signal line of the NOR circuit 1. The transfer gate 7 is interrupted when a clock ϕ2 is '0' and an output signal B from the NAND circuit 2 is placed on the output signal line thereof. The transfer gate 7 is conducted when the clock ϕ2 is '1' and a signal D from an inverter 6 is placed on the output signal line of the NAND circuit 2. |
