| 摘要 |
A NOR decode circuit which includes a latch composed of a pair of n-channel transistors and a pair of p-channel transistors with the p-channel transistor of one latch portion coupled to a reference circuit transistor via a first pass transistor and the p-channel transistor of the other latch portion coupled to the address select line controlled transistors via a second pass transistor. The pass transistors are also controlled by an enable row (ENROW) signal. The address transistors are larger and conduct more current than the reference transistor. When ENROW is activated, the n-channel transistors of the latch are enabled and current passes through one side of the latch circuit and through a third transistor in parallel with the address transistors if any of the address transistors are turned on. Current also flows through the other side of the latch circuit and through a fourth transistor in parallel with the reference transistor. The second pass transistor conducts a current I1 plus the current through the reference transistor (Iref) and the first pass transistor conducts a current I1 plus the current through an address transistor (nIref). Therefore, the second pass transistor conducts a current I1+Iref and the first pass transistor conducts a current I1+nIref. The difference between these currents, i.e. (n-1)Iref, is amplified by the latch, causing the row line to remain low when an address transistor is selected and causing the row line to be high when none of the address transistors is selected.
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