| 摘要 |
A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer.
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