| 摘要 |
A monolithic output stage which is self-protected against the occurrence of incidental latch-up phenomena and integrated in a portion of a semiconductor material chip which is isolated by a peripheral barrier structure linked electrically to a terminal (Vcc), specifically a supply terminal being applied thereto a constant voltage (+Vcc), has the barrier structure coupled to the terminal (Vcc) through a forward biased diode (D1) from the terminal (Vcc). The integrated barrier structure is formed within a region (21'') having a first type of conductivity, and comprises a heavily doped well (29) having the first type of conductivity and a substantially annular shape and contacting a large surface of the chip (22). This structure is characterized in that, in at least one portion thereof close to contact regions (S) for connection to said terminal (Vcc), the barrier well (29) is split into first and second heavily doped concentrical regions (29' and 29'') having the first type of conductivity. The barrier structure further comprises, located at said portion, an intermediate region (30) which is less heavily doped and also has the first type of conductivity, and a surface region (31) with a second type of conductivity located within said intermediate region. The invention preferably involves a power output stage including a vertical PNP transistor isolated by said barrier well. <IMAGE> |
