发明名称 |
Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing |
摘要 |
A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
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申请公布号 |
US5544105(A) |
申请公布日期 |
1996.08.06 |
申请号 |
US19940271691 |
申请日期 |
1994.07.07 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HIROSE, TOSHIHIKO;OHBAYASHI, SHIGEKI;KONDO, SETSU;HAYASAKA, TAKASHI;FUJINO, YOSHIYUKI;IKETANI, MASAYUKI |
分类号 |
G11C11/41;G11C7/14;G11C7/22;G11C11/401;G11C11/407;G11C11/417;G11C11/419;G11C29/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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