| 摘要 |
<p>The communications processor of the present invention comprises, in a single integrated circuit chip, the combination of a central processing unit (CPU-200)) having an execution unit (206) with an arithmetic logic unit and accumulators, a program counter, memory (400), a clock generator (202), a timer (212), a bus interface (204), chip select (210) outputs, and an interrupt processor (214); a digital signal processor (DSP-300) having an instruction set to carry out a digital signal processing algorithm, an execution unit for carrying out multiply and accumulate operations and an external interface; an address bus (102) connected between the CPU and the DSP; a data bus (104) connected between the CPU and the DSP; and a static scheduler for statically scheduling execution of the signal processing algorithm between the digital signal processor and the CPU. <IMAGE></p> |
