| 摘要 |
a phase synchronization loop for locking an input horizontal sync signal at a reference frequency; a control signal output means for counting one period of the horizontal sync signal locked by the phase sync loop, calculating a reduction period by dividing the counted horizontal sync signal with the pulse width modulation resolution, and reducing the high duty of the screen state control mode and the horizontal sync time to generate a control signal; and an output means for locking and outputting a pulse width modulation output according to each screen state control mode together with the horizontal sync signal.
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