| 摘要 |
PURPOSE: To improve an integration degree and to reduce parasitic capacity by reducing the area required for realizing a multi-port memory in a transistor array. CONSTITUTION: PMOS transistors 123, 128 are formed respectively on PMOS transistors of a seventh row and an eighth row of a transistor array of a third row. The drain area D128 of the PMOS transistor 128 is shared with the drain area D123 of the PMOS transistor 123. The PMOS transistor 128 can be connected in parallel to the PMOS transistor 123 without increasing the area of the transistor array. Connection capacity viewing from a read-out bit line 192 is not increased compared with the case when no PMOS transistor 128 is provided. The power driving the read-out bit line 192 to an 'H' is enhanced. |
