| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a synchronization system mounted with a plurality of ASICs to be driven with the same clock for preventing any timing error between the ASICs, and for surely transferring data. <P>SOLUTION: An ASIC1 in the pre-stage of a synchronization system 100 is provided with an expected value storage circuit 3 which stores the expected value of an input signal to the input register 40 of an ASIC 2 in the post-stage correspondingly to the output singal of an output register 30, an expected value comparing circuit 4 which compares the output signal of the input register 40 of the ASIC 2 with the expected value stored in the expected value storing part 3, a delay control circuit 5 which adjusts the delay quantity of a clock signal to be supplied to the output register on the basis of the comparison result of the expected value comparing circuit 4, and a clock correcting circuit 6 which generates a plurality of delay clock signals whose delay time to a reference clock signal is different, and selects the delay clock signal corresponding to the delay quantity adjusted by the delay control circuit 5 from among the generated plurality of delay clock signals, and supplies it to the output register 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
