发明名称 MEMORY MODULE AND DATA PROCESSOR
摘要 PURPOSE: To decrease the number of memories to be mounted on a memory module by constructing a memory devices for parity bits. CONSTITUTION: When 8 pieces of DRAM 101, 102, 104, 105, 106, 107, 109 and 110 of (1M-word×4-bit) output constitution are mounted on a packing substrate, 2 pieces of DRAM 103 and 108 of (1-word×2-bit) output constitution are mounted as the parity bit memory devices. Thereby, a single module of (1M- word×36-bit) output constitution is obtained. Thus, the DRAM devices of (1M- word×2-bit) constitution are applied for parity bits so that the number of DRAM devices can be decreased and a packing substrate can be used in common among the modules of (2M-word×36-bit) output constitution.
申请公布号 JPH08190511(A) 申请公布日期 1996.07.23
申请号 JP19950016477 申请日期 1995.01.06
申请人 HITACHI LTD;HITACHI TOBU SEMICONDUCTOR LTD 发明人 KANNO TOSHIO;YAMAZAKI KAZUO;YANAGISAWA KAZUMASA;FUJIMAKI MASAYUKI
分类号 G06F12/16;G11C5/00;(IPC1-7):G06F12/16 主分类号 G06F12/16
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