发明名称 CONFIGURABLE ARCHITECTURE FOR VIRTUAL SOCKET CLIENT TO AN ON-CHIP BUS INTERFACE BLOCK
摘要 An interface block provides an interface between an internal bus of an integrated circuit and a socket of a logic block. The interface block includes a synchronization module that performs any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block. A translation module provides translation of block encoding of the data for data transferred between the internal bus and the socket of the logic block. A queue module buffers data flowing between the internal bus and the socket of the logic block. A driver module handles low level and electrical drive specifications of the internal bus.
申请公布号 US2007088872(A1) 申请公布日期 2007.04.19
申请号 US20060533499 申请日期 2006.09.20
申请人 RHEE QUE-WON 发明人 RHEE QUE-WON
分类号 G06F5/00 主分类号 G06F5/00
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