发明名称 DATA PROCESSOR
摘要 PURPOSE: To provide a data processor capable of preventing the continuous operation of a specific mode when a normal mode is switched to the specific mode in error. CONSTITUTION: The data processor is provided with a power ON clear circuit 1 for outputting an initializing signal at the time of turning on a power supply, a flip flop 2 allowed to output a specific mode signal 102 at the time of turning on the power supply and to be reset at the time of resetting the specific mode, a NAND circuit 5, a timer 6 driven at the time of the specific mode, and when a specific mode continuation request signal is not outputted, capable of resetting the specific mode and outputting an internal reset signal 104, NOR circuits 7, 15, an inverter 8, a user ROM 10 including a user program in it, a specific mode ROM 11 including a program to be used in the specific mode, a switch 12, an instruction latch 13, a CPU 14, and an input block 9 for outputting the level state of a mode input terminal 16 to a CPU 14 at the time of a test mode.
申请公布号 JPH08185331(A) 申请公布日期 1996.07.16
申请号 JP19940327228 申请日期 1994.12.28
申请人 NEC CORP 发明人 OGATA YUKIHISA
分类号 G01R31/28;G01R31/3185;G06F11/22 主分类号 G01R31/28
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