发明名称 MEMORY ROW ARCHITECTURE HAVING MEMORY ROW REDUNDANCY REPAIR FUNCTION
摘要 The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module.
申请公布号 US2008316845(A1) 申请公布日期 2008.12.25
申请号 US20070829088 申请日期 2007.07.27
申请人 WANG SHIH-HSING;YUAN DER-MIN 发明人 WANG SHIH-HSING;YUAN DER-MIN
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
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