发明名称 Increased Switching Cycle Resistive Memory Element
摘要 An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer.
申请公布号 US2009027944(A1) 申请公布日期 2009.01.29
申请号 US20070782525 申请日期 2007.07.24
申请人 UFERT KLAUS 发明人 UFERT KLAUS
分类号 G11C11/00;H01L21/328 主分类号 G11C11/00
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