Parallel phase-locked loop oscillator circuits with average frequency calculation of input stage loop

摘要

A phase-locked oscillator circuit with a broad pull-in frequency range generates a stable output signal synchronized to the phase of an input signal. An input-stage phase-locking circuit wherein the phase of a first frequency-converted output signal from a 1st frequency-conversion section is compared by a 1st phase-comparison circuit with the phase of the input signal and the phase of the 1st frequency-converted output signal is controlled. A processing section determines the frequency component of the input signal based on the phase-comparison output signal from the 1st phase-comparison circuit. An output-stage phase-locking circuit compares the phase of a 2nd frequency-conversion section with the phase of the input signal in a 2nd phase-comparison circuit. The phase of the 2nd frequency-conversion section is controlled based on the resulting phase-comparison output signal and the phase comparison output signal from the 1st phase-comparison circuit. Thus, the phase of the 2nd frequency-converted output signal is controlled.