发明名称 |
FRAME ALIGNMENT CIRCUIT AND ENCODING/DECODING PROCESSING CIRCUIT USING THE CIRCUIT |
摘要 |
PURPOSE: To shorten alignment recovery time and to evade erroneous alignment by detecting an auxiliary bit from input encoded data, utilizing the detected output and detecting a frame bit from the input encoded data. CONSTITUTION: An encoding processing part 2 inserts the auxiliary bit and the frame bit to data scrambled in a scramble part 1 and performs encoding. A comparison part 41 compares (i)-th and (i+1)-th encoded data inputted from a digital transmission line and detects the auxiliary bit. A frame alignment detection part 43 generates the output timing of frame information and the frame bit, generates the information for setting and resetting a descramble part 5 and generates frame protective information. An alignment protective part 44 protects frame alignment and outputs the alarm of the frame alignment. The descramble part 5 returns the scrambled data to original digital signals and a decoding processing part 6 eliminates the auxiliary bit and the frame bit of the encoded data. |
申请公布号 |
JPH08172432(A) |
申请公布日期 |
1996.07.02 |
申请号 |
JP19940317176 |
申请日期 |
1994.12.20 |
申请人 |
FUJITSU LTD |
发明人 |
ISHIZUKA ATSUO;NAKAMURA NORIKAZU;CHIN SEIGEN |
分类号 |
H04L25/49;H04L7/00;H04L7/08 |
主分类号 |
H04L25/49 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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