Built-in self-test global clock drive architecture

摘要

A BIST clock driver for providing memory elements in a combinational and sequential logic circuit with a global clock signal during user mode and a test clock signal during testing. The clock driver also supplies clock signals to memory circuits that have clock inputs supplied by random logic. The clock driver supplies the random logic with a global clock signal. A clock multiplexor receives the generated clock and the test clock signal and provides the memory element with the generated clock signal during user mode and the test clock during testing of the memory element.