发明名称 |
Method and apparatus for reducing power consumption in memory circuits |
摘要 |
A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).
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申请公布号 |
US5530676(A) |
申请公布日期 |
1996.06.25 |
申请号 |
US19950379807 |
申请日期 |
1995.01.27 |
申请人 |
MOTOROLA, INC. |
发明人 |
SULLIVAN, STEVEN C.;BRAUER, MICHAEL L. |
分类号 |
G11C7/22;G11C8/18;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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