| 摘要 |
PURPOSE: To correctly output the signal that converges the error of the frequency or phase at a high communication speed by integrating the charge pump output to eliminate the unnecessary high frequency components and securing the necessary information. CONSTITUTION: The output charge CH of a charge pump 12 is supplied to a capacitor 153 in response to a single up-pulse *UP of the output of an error converging pulse generation circuit 11, and this charge value is increased so that the output potential VO of an integration circuit 15 is reduced. As a result, the input potential of a voltage control oscillator 14 rises and then the output frequency of this oscillator rises. On the other hand, the charge CH is discharged to the power supply line of a potential- VCC in response to a down-pulse DWN. Thus the frequency error of a regenerated clock CLK is converged in a prescribed range against the series signal DAT, and the phase error is converged to the fixed value. Furthermore, the charge CH including the unnecessary high frequency components is integrated by the circuit 15 so that these components are eliminated and only the necessary information are outputted. Therefore, the influences of the parasitic inductance and capacity of an external terminal 23 are reduced and the waveform distortions of the output of the terminal 23 are decreased. |
