发明名称 CLOCK REPRODUCTION CIRCUIT AND COMMUNICATION EQUIPMENT USING THE SAME
摘要 PURPOSE: To obtain a stable reproduced clock by performing the fast pull-in of a clock and reducing a jitter in a circuit provided with a function to reproduce the clock. CONSTITUTION: An inputted angle modulated wave is quantized by a phase quantizing means 2, and an eye pattern representing the change quantity of a phase in one symbol time can be obtained by a phase data delay means 3 and an arithmetic means 4. Plural detection values are set from the eye pattern, and timings to show the values are detected by a detecting means 5. The timing (A) requiring correction out of detected timings is corrected by delaying by a timing delay means 6, and AND with the timing (B) without requiring correction is taken, and the clock in which a fast operation can be performed and the jitter can be reduced is reproduced at such timing by a phase locked loop 8.
申请公布号 JPH08163194(A) 申请公布日期 1996.06.21
申请号 JP19940304569 申请日期 1994.12.08
申请人 HITACHI LTD 发明人 SHIMODA SHINICHI;SUDO SHIGEYUKI;SUZUKI AKIHIRO
分类号 H04L27/22;H04L7/00 主分类号 H04L27/22
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