Verfahren zur Herstellung von Bauelementen mit übereinander angeordneten Feldeffekttransistoren mit Wolfram-Gitter und sich daraus ergebende Struktur.

摘要

A stacked semiconductor structure including: a base structure comprised of a semiconductor substrate (18/19) having active regions (21) of devices (N1, ...) formed therein and a plurality of polysilicon lines (23-1, ...) formed thereupon; a first thick passivating layer (26/27) formed onto said substrate having a set of first metal contact studs (30-1, ...) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, ...), the upper part of said first contact studs defining either gate electrodes of sPFET devices (P2) and/or interconnection conductors; the surface of said first metal contact studs is coplanar with the surface of said first thick passivating layer; a thin insulating layer (31) forming the gate dielectric layer of said PFET devices and provided with contact openings (32-1, ...) to expose desired portions of said first contact studs at desired locations; a plurality of polysilicon lands (33-1, ...) formed over said thin insulating layer (31), a certain portion thereof define the source, drain and channel region of the body of a determined PFET device (P2); at least one of said source and drain regions contacting a first metal contact stud (30-4) through a contact opening; a second thick passivating layer (35/36) having a set of second metal contact studs (38-1, ...) therein contacting at least one of said polysilicon lands (33-1, ...) and/or said first contact studs (30-1, ...); the surface of said second metal contact studs is coplanar with the surface of said second passivating layer. a first metal interconnection configuration having metal lands (39-1, ...) electrically contacting at least one of said second metal contact studs (38-1, ...); and a final insulating film (40). The structure of the present invention can be advantageously used in chips implementing 6D SRAM cells with stacked PFETs as load devices in CMOS FET technology.