| 摘要 |
<p>An MPEG-2 decoder circuit achieves smaller circuit area, and hence lower cost, by using circuitry (111), including ROMs (137), designed to implement residue arithmetic to calculate discrete cosine transform in a pipeline or interactive fashion. A variable length decoder based ROM-like PLA (109) parses the stream of data to separate audio from video data and to direct the necessary operations on the data elements. The decoder (104) and data flow through the system are controlled by a condition move processor (107), which is implemented as a data memory (414).</p> |
