发明名称 |
INTERLOCK CONTROL SYSTEM BETWEEN MULTIPLEX LOAD CONTROLLERS |
摘要 |
<p>PURPOSE: To quickly set or revise data almost without an artificial operation by storing an address of a terminal equipment and interlocking conversion data corresponding to interlock control of prescribed control designation data in a rewritable way. CONSTITUTION: A load interlocking conversion data registration memory 71A to relate each management point of both common share memories 74A, 74B is provided to a main CPU 71. Addresses of terminals 50A, 50B sent from a load controller 30A together with a control signal and interlocking conversion data relating to interlocking control with control designation data to be returned to the load controller 30B are stored in the memory 71A in a rewritable way. Furthermore, a storage area of the common share memories is divided into four blocks and addresses are registered equally to the blocks. The four logic numbers are set based on ON/OFF/invalid operations and registered in the common share memory 74B while being divided into each control class.</p> |
申请公布号 |
JPH08154283(A) |
申请公布日期 |
1996.06.11 |
申请号 |
JP19940291852 |
申请日期 |
1994.11.25 |
申请人 |
MATSUSHITA ELECTRIC WORKS LTD |
发明人 |
KURITANI TAKASHI;FUKUNAGA MASAKAZU |
分类号 |
H05B37/02;H04Q9/00;(IPC1-7):H04Q9/00 |
主分类号 |
H05B37/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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