| 摘要 |
PURPOSE: To eliminate the mixed noises and to reduce the error rate of communication data by dividing the pulse received from a PLL circuit, inputting these divided pulses to a latch means after the timing adjustment, and latching the pulses at the center of a reproduced data pulse. CONSTITUTION: An absolute value circuit 8 uses only the positive peak signals among positive and negative peak signals of the delay detection signals whose high frequency components are deleted by an LPF 5. A comparing part 9 compares the positive peak signals with a reference level Ref and outputs a reproduced data pulse to input it to a PLL circuit 10. The circuit 10 produces a pulse that has the synchronization of phase with the reproduced data pulse received from the part 9, and this pulse is divided by a frequency divider 16. A clock signal generator part 15 adjusts the timing and generates a timing clock against the divided and inputted pulses. Then the timing clock is inputted to a latch part 7 as a latch signal, and the part 7 latches the reproduced data pulse of the part 6 and demodulates the data. |
